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Always on - The power aware security IP SoC verification challenge

White Paper Published By: Freescale Semiconductor
Freescale Semiconductor
Published:  Jun 02, 2011
Type:  White Paper
Length:  4 pages

The increasing demand for secure data traffic has found itself into almost every networking processor available on today's market. This growing demand has led to some innovations in the field of cryptography that impose some implementation and verification challenges, especially in large SoCs. One such feature is the need to keep keys, counters and other cryptographic data, hidden, protected and unique for every device. This can be done by using a non-volatile memory that is connected to a continuous power supply, independent from the rest of the device, equipped with protective mechanisms to secure the cryptographic data. A device of this type poses a challenge to the SoC verification, it needs to be verified during stages of the device's life that are not normally covered by monitors and checkers, before power-on reset is asserted for example. It may also have an adverse effect on the device's reset sequence and vice versa. All these are not a part of the traditional verification flow and in fact regular verification does not usually simulate any power aspects of the design.



Tags : 
power, system on chip, security